Digital Electronics and Embedded Systems - 4EU7ENS9

Number of hours
- Lectures 14.0
- Projects -
- Tutorials 8.0
- Internship -
- Laboratory works 38.0
- Written tests -
ECTS
ECTS 5.0

Goal(s)

Understanding the operation mechanisms of embedded systems for the control of electrical systems with application to power electric grid :
• digital electronics, VHDL
• Programming of control "real-time" systems applied to the protection of grid.

Responsible(s)

Mathias VOISIN FRADIN

Content(s)

Part « digital electronics, VHDL»
* Course (8 hours) :
- MOS transistors and elementary gate
   - Logic gates and flip-flops - temporal aspects
   - VHDL and Moore Machines
   - Methodological tools of VHDL desig- Transistors MOS et porte élémentaire
* lab works (12h):
- Moore machine - VHDL - programmed counter
   - Methodological tools, VHDL, MEF - realization of a CAN
   - 1st order filter (VHDL, MEF, CAN, CNA)

Part « computer structures and real-time development software for embedded systems»
* Course (10 hours) :
Equipment architecture :
- number state,
- basic computer structure,
- processor structure
- main evolution and architecture (DSP-mC-IPs),
- language level and programming.
Software architecture :
- task definition,
- external events management,
- interrupt service routine organisation (PIC example),
* Real time computing desk (4h) and lab works (26 hours) :
- operations with I / O
- Implementation of interruption mechanisms
- fixed-point Data encoding,
- Experimental implementation of an industrial example: protection discrimination of a power grid (« smart grid »)
Real monitor testing using Code Composer Studio on a Texas Instruments DSP

Prerequisites

Digital electronic circuits
Module intégrateur « ASI/IEE/SICOM » 1A,
Module d'Approfondissement IEE-1A
Module « Electronique et signaux numériques »,
Module « informatique »

Test

Session normale / First session
Evaluation Non rattrapable (EN)/ EN assessment: 50%
- BE Electronique numérique et VHDL / BE digital electronics and VHDL: 25%
- BE informatique industrielle / BE industrial computer science: 25%
Evaluation Rattrapable (ER) / ER assessment :
Contrôles individuels en temps limité / Individual tests in limited time
- Electronique numérique et VHDL / BE digital electronics and VHDL: 10%
- Informatique industrielle / industrial computing part : 40%
Session de rattrapage / Second session:
La note de session de rattrapage remplace la note de ER. Le EN n'est pas rattrapable/ The new mark will replace the first one (ER). No resitting for the EN exam (lab works).

Moyenne de l’UE / Course Unit assessment = EN 50% + ER 50%

Calendar

The course exists in the following branches: