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Ecole nationale supérieure de l'Énergie, l'Eau et l'Environnement
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Engineering school in energy, water and environment

> Studies > E3-STU-COURSES

Design Models for Power Electronics - 5EU9DMP9

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Number of hours
- Lectures : 8.0
- Tutorials : 8.0
- Laboratory works : 44.0
- Projects : -
- Internship : -
ECTS : 5.0
Officials : Jean-Luc SCHANEN

Goals

The aim is to provide students with a deep understanding of the main phenomena that are faced when designing a power electronics converter: designing passive elements, evacuating the semiconductor losses, and dealing with ElectroMagnetic Compatibility issues.
The understanding of the phenomena is facilitated by dedcated labworks (experimental or simulations). All design models are used in a final project

Content

thermal design aims to understand the origin of semiconductor losses, givig mathematical models to evaluate them, understanding the performances of various heatsinks, being ableto choose and characterize them (8h00 flipped classroom, 8h00 labwork).
Passive design: through a basic study case of a DC-DC filter design,the students will learn the main characteristics necessary to choose capacitors, and associated simple models. On the main example, the design of an inductor will be adressed, based on the area product method. Losses evaluation will also beconsidered (Steinmetz equation) (12 hours project)
EMC aspects will be teached through both theoretical and practical part, the main aim being to be able to understand the phenomena, and to know how to size an EMC filter for Switched Mode Power Suply. stray elements of passive elemenst and interconnects will be studied. (8h00 lecture, 8h00 labwork)
Final project (16h00) will use all previous design models into a full design process of a DC-DC converter, under EMC and losses constraints. Desgn by optimization will be carried out to obtian the minimal mass of the converter.

Prerequisites

Power Electronics basics (chopper, inverter)
Electrical Circuit basics

Tests

Session normale / First session
Contrôle continu / Continous assessment (CC) : rapport de synthèse sur le projet, notes sur les BE Thermal, Magnetics et CEM
Contrôle terminal / Final exam (CT) : QCM de connaissances

Session de rattrapage/ Second session
La note obtenue remplace la note de CT / Another exam will replace the first one (CT)
Le CC n'est pas rattrapable / No retake for CC

CC 65% (15% for each part + 20%final project) + CT 35%

The exam is given in english only

Calendar

The course exists in the following branches:

Curriculum - Master's Degree in Engineering IEE - Semester 9 (this course is given in english only )
Curriculum - Master inter SGB - Semester 9 (this course is given in english only )